Application of ETX module on CPCI bus CPU card

0 Preface

Computers used under certain conditions (such as harsh environment, military application environment conditions) have higher and stricter requirements than ordinary commercial computers in the following aspects: climate, mechanical and electromagnetic environment adaptability, reliability Usability, maintainability, operability, human-computer interaction performance, small size, light weight, low power consumption, scalability, easy upgrade and long service life.

In some applications, there are some specific requirements. For example, some loading platforms, such as on-board and airborne platforms, usually require corresponding requirements for installation space (volume, shape), and also require front maintenance; In some application requirements, the types and number of user interfaces are large, and general commercial computers cannot meet the requirements.

At present, in most cases, appropriate mature commercial computers are used for day-to-day reinforcement, and corresponding reinforcement measures are adopted to improve the adaptability of the mechanical environment, the climatic environment and the electromagnetic environment to adapt to the application of specific environments such as harsh environments and military environments. There is an on-board computer in the ground system of the XX project that I undertake. Due to the space limitation of the vehicle platform, the on-board computer is required to use a 3U card, and the number and number of interfaces required by the user are much more than that of a general commercial computer. Find a ready-made CPU card commercial product, for which you have to develop this card yourself. The other components of the on-board computer are as much as possible using commercial off-the-shelf products for day-to-day reinforcement.

1 CPU card design

1.1 Based on ETX module

Usually, the CPU card design uses a separate central processor chip and a matching chipset, which has a high development cost and a long development cycle. The on-board computer developed by this project has low development cost and tight development cycle. The CPU card design scheme based on ETX module can solve this problem better. ETX's module can be seen as a special chip that integrates CPU, PCI bus, ISA bus and standard PC/IO functions. ETX module has high performance, low power consumption, small size, and a PC is fully compatible for easy upgrade and vibration resistance. Good, different grades of CPU can be selected and so on. Using ETX module can simplify CPU card design, save development costs, and shorten development cycle.

ETX (embedded technology extended) is an embedded PC standard that is firstly defined and promoted in the industry by the famous German embedded industrial PC product supplier JUMPTEC Group. ETX module products must be used together with the user's PCB substrate. All ETX modules are connected to the user-designed PCB substrate via the standard ETX-BUS (4 x 100pin) on the back. ETX - BUS defines standard PCI, ISA bus signals, USB, sound card, VGA, LCD, Video, COM1, COM2, LPT, FLOPPY, IRDA, Mouse/Keyboard, IDE1, IDE2, Ethernet and other signals.

1.2 CPU card basic structure

The basic structure of the CPU card is shown in Figure 1. It can be divided into ETX module, bridge chip, bus interface, I/O interface, and so on.

CPU card basic structure

1.3 Design requirements

(1) The CPCI bus CPU card design based on the ETX module is key to developing the ETX-CPCI carrier board, converting the PCI bus provided by the ETX module to the CPCI bus on the carrier board, and passing as many interfaces as possible through the JPCI of the CPCI. Transfer to the rear panel and keep the front panel VGA, PS/2, LAN, USB interface for debugging. An IDE interface is retained on the CPU card in the form of a 44 pin, and the electronic disk is connected according to system configuration requirements. The other IDE interface is transferred to the rear panel via J2 to connect peripherals such as the optical drive.

(2) Fully consider the need for future expansion and user demand changes. The CPU card design should lead as many interfaces as possible to the rear wiring board, and the switch board design can be changed in the future according to user requirements.

(3) Component layout and wiring should fully consider the reliability and anti-interference ability of signal switching. The layout of the power supply and the ground should be considered as much as possible in the circuit layout. In the 8-layer PCB, there are separate power and ground planes. Since there are multiple power supplies, such as 3.3V, 5V, and 12V, the devices of the same power supply should be placed together as much as possible to facilitate the division between different power sources in the power layer. At the same time, the stratum should be divided. For example, there should be no electrical ground beneath the chip 169 000 to avoid introducing interference. Decoupling capacitors must be added to each chip to minimize interference.

(4) The electrical connection of the I/O interface and module is plugged and unplugged to facilitate upgrade and easy maintenance.

2 CPU card component design

2.1 ETX interface connector and interface signal description

The ETX transmits various signals using four 100pin models for the FX8-S100, as shown in Figures 2 and 3.

The FX8-S100 connector is a surface mount soldering device that does not occupy the other trace layer space of the printed board. 100 pins are drawn, and the spacing between two adjacent pins is 0.25 mm. ETX provides a standard PCI bus signal group and a standard ISA bus signal group. The common interfaces provided by ETX include: two pairs of USB serial data lines for standard USB interfaces; two IDE interfaces; one parallel port, which can be reused as a floppy drive interface; PS/2 standard keyboard and mouse interface; two serial ports ; Ethernet interface signal; sound card interface signal; graphics card interface.

(1) Connector X1 is used to transmit PCI bus signals, USB signals and sound card signals;

(2) Connector X2 is used to transmit the ISA bus signal;

(3) Connector X3 is used to transmit VGA, LCD, Video, COM1, LPT/Foppy, IrDA and Mouse/Keyboard signals;

(4) Connector X4 is used to transmit IDE1, IDE2, Ethernet and characteristic signals. According to the above, the design plan is divided into: bridge chip and bus interface, I / O interface (IDE, VGA interface, serial port, keyboard and mouse interface, USB interface, network port, parallel port, floppy drive interface), rear routing Board and rear routing interface P2 and other parts.

2.2 bus bridge chip and bus interface

The bus interface provided by the ETX module is a PCI bus. The electrical difference between the PCI bus and the CPCI bus is mainly because the CPCI bus supports hot swap. However, the hot plug implementation of the CPCI bus CPU card requires not only a lot of work on the hardware, but also a lot of work on the software. In this design, the application of the CPU card hot plug is not considered. The PCI bus interface provided by the ETX module supports only 4 PCI peripheral slots. In a typical CPCI system, there must be at least 6 CPCI slots. Therefore, a bus bridge chip must be added in this design.

The role of the PCI-PCI bridge is to coordinate traffic between the two PCI local buses. Its role is to monitor all transactions initiated on these two PCI local buses and decide whether to transfer the transaction to another PCI local bus. When the bridge determines that a transaction on one bus needs to be transferred to another bus, the bridge must act as the bus target for initiating the transaction, as well as the master device of the target bus of the transaction. For the master device of the transaction (and the target of the transaction), the fact that the bridge resides between the starting bus and the target of the transaction is invisible.

In addition to determining if a transaction initiated on one bus needs to be transferred to another bus, the bridge also has the following features:

(1) The bridge monitors SERR# on the second bus, and if the sampling is valid, it is transmitted to SERR# of the first bus;

(2) The bridge monitors RST# on the second bus, and if the sampling is valid, it is transmitted to the RST# of the first bus;

(3) The bridge may have a device ROM containing its device driver, in which case the bridge must recognize and allow access to the ROM memory;

(4) A bridge may have a set of device-defined I/O or memory-mapped I/O registers that control the functionality of the bridge, in which case the bridge must recognize and allow access to those registers;

(5) The bridge may have a memory buffer, in which case the bridge must recognize and allow access to these registers.

During the selection process of the bridge chip, a PCI2050 chip produced by TI Company was found, which is compatible with the CPCIHot Swap protocol, which defines the process of inserting and removing the expansion card without affecting the system operation, that is, supporting the expansion board. Hot swapped and has an exchange diode indication. Choosing this chip prepares the innate hardware conditions for hot plugging of other expansion cards in the system.

The PCI2050 provides a high-performance PCI-PCI connection to the PCI bus. Data exchange is bridged between the master PCI bus and the target PCI bus. The device allows simultaneous data transfer on both ends of the bus. The two-way bridge transmissions are independent, and both support burst mode to increase data throughput. The PCI2050 supports a 32-bit expansion interface running at up to 33MHz and provides two levels of internal arbitration for up to four and nine secondary hosts, respectively. It is also pin-compatible with the Intel21150ab/ac and 2115bcPCI-PCI bridge chips, making it easy to replace the bridge chip without changing the original design. Available in a variety of space-saving packages, the 208-pin QFP package and the 209-pin MicroStar BGATM package are available. This design is the first contact bridge chip. For ease of debugging, we choose the 208-pin QFP package.

According to the PCI2050 data, the classification of each part of the foot function (PRIMARYPCI, SECONDARY - PCI, POWER, GND, CLOCKS, JTAG, ARBITER) is shown. The PCI2050 schematic library is shown in Figure 4.

The bridge chip's PRIMAR-PCI is primarily connected to the PCI interface signal provided by the ETX module. The SECONDARY-PCI interface portion of the bridge chip is primarily connected to the CPCI interface on the CPU card. However, it should be noted that the control signals of the CPCI bus must have pull-up resistors, in order to ensure that they still have stable values ​​without the device driver bus. Such signals are FRAME#, TEDY#, ERDY#, ERQ64#, and ACK64#. Point-to-point and 32-bit shared signals do not require pull-up resistors, and bus stops ensure their stability.

2.3 I/O interface

2.3.1 IDE interface

The Integrated Drive Circuit (IDE) is a general term for any drive with an integrated (built-in) disk controller. In fact, the official name of the IDE interface is ATA (AT Embedded Interface), which is also an ANSI standard. From a more precise point of view, it evolved from several different versions of the standard. Regardless of how you look at it, the IDE is generally suitable for any disk drive with a built-in controller.

IDE devices generally include hard drives, optical drives, and so on. Because the CPU card of this design is mainly used in computers that are resistant to harsh environments, the system guides the use of electronic disks. The operating temperature and vibration resistance of electronic disks are much better than ordinary hard disks, but the price of electronic disks is relatively expensive, and large-capacity electronic disks are also difficult to purchase. Therefore, the data disk in the system also needs to use the hard disk, and the heating method can make the hard disk work normally after the system starts for a certain period of time. Since the design of the heating circuit is beyond the scope of this article, the design method of the heating circuit will not be described in detail here.

The ETX module provides 2 IDE channels (PRAMARY IDE and SECONDARYIDE) with 2 IDE devices per channel. The interface of a normal IDE device is typically a 40-pin signal port, and the power to the IDE device is provided by a separate power connector. The IDE interface of the electronic disk is generally 44pin. The definition of the front 40pin is the same as that of the common IDE device. The last 4pin is the power supply interface of the electronic disk. The electronic disk uses only 5V. Therefore, in this design, the PRIMARYIDE-44pin interface is placed on the CPU card for connecting the electronic disk as a system disk. The SECONDARY IDE is connected to the regular hard disk or optical drive through the rear panel interface P2 to the rear panel.

The DASP signal is low when the IDE device is active (such as a read or write operation). Therefore, the signal can be connected to a light-emitting diode in series to indicate the active state of the IDE device, which is commonly referred to as a hard disk light. The circuit schematic of the hard disk light interface is shown in Figure 5.

2.3.2 VGA interface

The Video Graphics Array (VGA) was introduced by IBM in 1987 and is an analog system. The analog display is similar to the digital display, using RGB electron guns to create a variety of colors, but the various colors in the analog system can be displayed at different intensity levels, such as VGA with 64 levels to display colors. This variability produces a total of 262 144 colors (643), of which 256 colors can be displayed simultaneously. For actual computer graphics, the color level is usually more important than the high resolution, because the more colorful images are more realistic in the human eye. So VGA's analog image technology improves the system's ability to represent colors.

In this design, considering the convenience of debugging, a standard VGA interface is designed on the front edge of the CPU card, and the VGA signal is extracted by the BD15 hole type connector. At the same time, considering that this CPU card will generally be applied to the chassis of the weapon system specific rear-out structure, the VGA signal is also led to the rear panel interface P2.

2.3.3 Keyboard and mouse interface

To facilitate debugging, a standard PS/2 interface is designed on the front edge of the CPU card, and the keyboard and mouse signals are extracted from the PS/2 socket. At the same time, considering that this CPU card will generally be applied to the specific rear-outline structure of the weapon system, the keyboard and mouse signals are also led to the rear panel interface P2.

The 5V and GND in the PS/2 interface signal cannot be directly connected to 5V and GND on the CPU card and must be filtered and isolated before being connected. Otherwise, it is easy to introduce clutter caused by the operation of the keyboard and mouse input device to the CPU card.

2.3.4 Serial Port

The serial port signal provided by the ETX module conforms to the TTL signal. And our common serial signal generally follows the RS-232 standard.

The full name of the RS-232 standard (protocol) is the EIA-RS-232C standard. The EIARS-232C standard was originally customized for the remote communication connection data terminal equipment ETD (data terminal equipment) and the data communication equipment DCE (data communication equipment). Therefore, the development of this standard does not consider the application requirements of computer systems. But if you want to apply a near-end connection between a computer (more precisely, a computer interface) and a terminal or peripheral. Obviously, some of the provisions of this standard are inconsistent and even contradictory with computer systems. In addition, the “send” and “receive” mentioned in the EIA-RS-232C standard are defined in the DTE position rather than in the position of the DCE. Since in a computer system, information is often transferred between the CPU and the I/O device, both are DTEs, so both parties can send and receive. EIA-RS-232C specifies various signal line functions for electrical characteristics and logic levels as follows:

(1) On TxD and RxD:
Logic 1 (MARK) is -3v~-15v
Logic 0 (SPACE) is +3v~+15v

(5) On control lines such as RTS, CTS, DSR, DTR and DCD: the signal is valid (on, ON state, positive voltage) is +3v~+15 signal is invalid (open, OFF state, negative voltage) is - 3v~-15vEIA-RS-232C uses positive and negative voltages to indicate the logic state, which is different from the rule that the TTL indicates the logic state at high and low levels. Therefore, in order for a TTL device to be connected to a general-purpose serial device, the level and logic relationship must be changed between the EIA-RS-232C and the TTL circuit. The method of implementing this transformation can be a discrete component or an integrated circuit. At present, the widely used method is to apply integrated circuit conversion devices, such as UAM211E and SN75150 chips, to convert TTL level to EIA level.

Taking the UAM211E chip as an example, the pins 5, 6, 7, 8, 19, 20, 22, and 26 of the UAM211E are connected to the TTL input. Pins 1, 2, 3, 4, 9, 18, 23, 27 are terminated with an EIA-RS-232C. The ETX module provides a TTL signal, while the EIA-RS-232C signal requires an EIA high voltage. Therefore, all RS-232 output and input signals must pass through the UAM211E and level-transformed before being sent to or from the connector.

2.3.5 Network Port

The ETX module provides a 10BASE-T/100BASE-T adaptive Ethernet interface that requires a transformer with a 1:1 turn ratio for protection.

2.3.6 USB interface

USB (Universal Serial Bus) is an external device bus standard designed to provide plug-and-play functionality for externally connected devices on a PC. The emergence of USB eliminates the need for dedicated ports and reduces the use of dedicated I/O interfaces, saving significant resources like IRQ. All devices connected to a USB port require only one IRQ. So the USB interface in the current CPU card design is an indispensable interface.

An overcurrent protection device is typically used in the USB interface circuit to prevent system failure or crashes caused by damage to external USB devices or cables. The USB interface supports hot swapping, which is one of the biggest advantages of the USB interface. Generally, a capacitor with a large capacitance value should be placed at the power supply of the USB interface to absorb the transient surge of current caused by the hot plugging of the external USB device.

3 PCB design for CPCI boards

3.1 Component package selection

In this design, all electronic components use surface-mount components. Most of the resistors and capacitors are packaged in 0603, and a large number of resistor banks are used. Because it only welds on the surface, it does not require drilling. It is small in size, low in power consumption, saves space on the printed board, and simplifies the layout and routing of the whole plate.

3.2 PCB layer selection

This design chose to make an 8-layer PCB. The bus standard connector of the CPCI board has a pin pitch of 2.0mm, a pad aperture of 0.6mm, and a pad diameter of 1.1 mm, so the trace space between the two pads is only 0.9 mm, and the line width is 6 mils. The 6 mil line can only go 2 single layers, and the CPCI bus connector has 5 pins in a single row, that is, 5 wires must be taken, so the signal layer cannot be less than 3 layers. For a CPU card, its main power supply is 3.3V and 5V. In order to ensure the symmetry of the signal layer and the power layer, and considering the complexity of the board, the signal layer is designed as 4 layers and the electric layer is designed as 4 layers. The final layer distribution design of the printed board is the top layer signal layer, the 3.3V electric layer, the inner signal layer 1, the ground layer, the ground layer, the inner signal layer 2, the 5V electric layer, and the bottom signal layer, as shown in FIG. 6.

3.3 Component layout

The earliest thing to do in PCB design is to package the components and convert the connection information of only the function modules into the actual electrical connectors for the physical devices. The layout in the design is an important part. The quality of the layout directly affects the effect of the wiring, so in general, a reasonable layout is the first step in the success of PCB design. For this design, the first thing to consider is the placement of the ETX module, followed by the location of the external interface connector.

The shape of the ETX (90mm × 100mm) determines that it will occupy most of the space of the 3U CPCI board. Each interface connector can only be distributed on both edges of the printed board, as shown in Figure 7. Other resistors and capacitors can be distributed in the lower part of the ETX module without interfering with the ETX module because the surface mount component is selected to be less than 3mm in height. The chip is packaged high and is usually placed on the back of the printed board. The layout of components such as chips and resistors and capacitors mainly considers the ease of wiring, and the connection between components is as short as possible, taking into account the overall aesthetics.

3.4 PCB Circuit Design of CPCI Bus

In order to achieve a series of features of CPCI, there are a series of requirements for CPCI bus cards in the specification;

(1) PCB characteristic matching impedance is 65 ± 10%;

(2) Each power plane must be decoupled to ground in order to properly handle the impact of the switching current. Generally, there should be a 0.1uF capacitor for every 10 power pins.

(3) The bus signal line needs to use a 10 ± 5% termination matching resistor to minimize the effect of the termination on the card on the CPCI backplane. The resistor should be placed within 15.2 mm of the connector pin of the signal. Bus signals include AD0-31, C/BE0-3#, PAR, FRAME#, IRDY#, TRDY#, STOP#, LOCK#, IDSEL, DEVSEL#, PERR#, SERR# and RST#;

(4) The length of all bus signal terminations on the CPU card must be less than or equal to 1.5 inches. This length includes the length of the connector pins through the termination matching resistor to the bridge chip.

3.5 PCB design of other signal lines on the board

(1) The network port signal and the USB signal belong to the differential signal. The differential line should be applied when the line is printed on the printed board. For the network port signals TX+ and TX-, RX+ and RX-, the differential line pair is used. For the USB signal USB+ And USB - to use differential pairs;

(2) The electrical ground layer in the lower part of the network interface transformer chip should be dug to avoid introducing interference;

(3) IDE signal lines should be as long as possible to ensure transmission quality.

4 Conclusion

The ETX module provides a solution for the rapid development of 3U CPCI bus CPU cards with its powerful performance, high reliability, flexible structure, excellent scalability and small size. Through in-depth analysis of CPCI bus characteristics and a deep understanding of high-frequency digital circuit design methods, a 3U CPCI bus CPU card based on ETX module has been successfully developed. The comprehensive test and practical application verification show that the card has reached the performance requirements required by the system, the system works stably, and the interfaces are applied normally.

(Text / North China Institute of Computing Technology, Lu Wei)

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